The TXMC638 is a standard single-width Switched Mezzanine Card (XMC) compatible module providing a user configurable Kintex-7 FPGA with 24 ADC input channels.
The TXMC638 ADC input channels are based on the Linear Dual 16-Bit 5Msps Differential LTC2323-16 ADCs. Each of the 24 channels has 16bit resolution and works with up to 5Msps. The analog input circuit is designed to allow input voltages up to ±2.5 V on each input-pin resulting in a ±5 V differential voltage range.
For customer specific I/O extension or inter-board communication, the TXMC638 provides 64 I/Os on P14 and 4 Multi-Gigabit-Transceiver on P16. The P14 I/O lines are connected directly to the FPGA and can be used as 64 single ended LVCMOS24 or as 32 differential LVDS25 interfaces. Additionally the TXMC638 provides three 100 Ohm terminated ac-coupled, differential inputs with wide Input voltage range.
All front I/O lines such as the ADC interface and the three 100 Ohm inputs are connected to a 98-pin. Samtec ERF8-049 Rugged EdgeRate Connector.
A 1GB, 32 bit wide DDR3 SDRAM is connected to the user FPGA. The SDRAM-Interface uses an internal Memory Controller of the Kintex-7.
The user FPGA is configured by a serial SPI flash. For full PCIe specification compliance, the XILINX Tandem Configuration Feature can be used for FPGA configuration. XILINX Tandem Methodologies “Tandem PROM” is the favored methodology. The SPI flash device is in-system programmable. An in-circuit debugging option is available via a JTAG header for read back and real-time debugging of the FPGA design (using Xilinx “ChipScope”).
User applications for the TXMC638 with Kintex-7 FPGA can be developed using the design software Vivado Design Suite. A license for the Vivado Design Suite design tool is required.
TEWS offers a well-documented FPGA Board Reference Design. It includes constraint file with all necessary pin assignments and basic timing constraints. The FPGA Board Reference Design covers the main functionalities of the TXMC638.
The TXMC638 is delivered with the FPGA Board Reference Design. The user FPGA can be programmed via the on-board Board Configuration Controller (BCC). Programming via the JTAG interface using an XILINX USB programmer is also possible. In accordance with the PCI specification and the buffering of PCI header data, the contents of the user FPGA can be changed during operation.
Features
- Standard XMC module
- User configurable FPGA (Xilinx Kintex-7)
- 1 Gbyte, 32 bit wide DDR3 SDRAM
- 24 channels 16 bit ADC
- Offering single-ended and differential mode
- single-ended voltage input ranges (±2.5 V)
- differential voltage input ranges (±5 V)
- Sampling rate up to 5 Msps
- Digital rear I/O
- 64 single ended digital I/O lines (LVCMOS24)
- or 32 differential digital I/O lines (LVDS25)
- Front panel I/O (Rugged EdgeRate connector) and rear I/O via P14 and P16
Ordering Options
| Manuf. Part No | | Part Description |
| TXMC638-10R | | Kintex-7 FPGA XC7K160T-2 FBG676, 1GBDDR3, 24x Analog In and 64 direct FPGA Back I/O Lines on P14, 4 MGTs on P16 |
| TXMC638-11R | | Kintex-7 FPGA XC7K325T-2 FBG676, 1GBDDR3, 24x Analog In and 64 direct FPGA Back I/O Lines on P14, 4 MGTs on P16 |
| TXMC638-12R | | Kintex-7 FPGA XC7K410T-2 FBG676, 1GBDDR3, 24x Analog In and 64 direct FPGA Back I/O Lines on P14, 4 MGTs on P16 |
Manuals and Accessories
| Manuf. Part No | | Part Description |
| TXMC638-DOC | | User Manual |
| TA310 | | Cable Kit for Modules with Samtec ERF8-049-Connector TEWS |
| TDRV018-SW-25 | | Integrity Software Support |
| TDRV018-SW-42 | | VxWorks Software Support (Legacy and VxBus-Enabled Software Support) |
| TDRV018-SW-65 | | Windows Software Support |
| TDRV018-SW-82 | | Linux Software Support |
| TDRV018-SW-95 | | QNX Software Support |
For Software Options please contact systerra.
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