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TXMC637

NEW - Reconfigurable FPGA with 16 x Analog Input 8 x Analog Output and 32 Digital I/O

The TXMC637 is a standard single-width Switched Mezzanine Card (XMC) compatible module providing a user configurable FPGA (AMD Artix 7 ™).

32 ADC input channels, based on four ADAS3022, can be software configured in groups to operate in single-ended or differential mode. Each of the 32 channels has a resolution of 16bit and can work with up to 1 MSPS. The programmable gain amplifier is software configurable and allows a full-scale input voltage range of up to +/-10.24V.

The TXMC637 DAC output channels are based on the Dual 16 bit AD5547 DAC. Each DAC output is designed as a configurable single-ended bipolar analog output. Output voltage is configurable as ±10.0V, ±5.0V or ±2.5V.

32 ESD-protected TTL lines provide a flexible digital interface. All I/O lines are individually programmable either as input or output. Input I/O lines are tri-stated and could be used with the on-board pull up or as tri-stated output. Each TTL I/O line has a pull resistor sourced by a common pull source. The pull voltage level is selectable to be either +3.3V, +5V and additionally GND.

16 of these ESD-protected TTL lines can be configured to be either a TTL interface or RS422 interface. Switching is done via the User FPGA. All 8 RS422 transceivers have individual internal switchable terminations.

The User FPGA is connected to a 512 Mbytes, 16 bit wide DDR3L SDRAM. (to be used with the AMD Memory Interface Generator)

For customer specific I/O extension or inter-board communication, the TXMC637 provides 64 FPGA I/Os on P14 (directly connected) and 4 FPGA Multi-Gigabit-Transceivers on P16. All P14 I/O lines can be configured in accordance with 7-Series SelectI/O features e.g. as 64 single ended LVCMOS25 or as 32 differential LVDS25 interface.

The User FPGA is configured by a serial quad SPI flash. For full PCIe specification compliance, the AMD Tandem Configuration Feature can be required for FPGA configuration. AMD Tandem Methodologies “Tandem PROM” should be the favored Methodology. The SPI flash device is in-system programmable. An in-circuit debugging option is available via a JTAG header for (real-time) debugging of the FPGA design.

User applications for the TXMC637 with Artix™ 7 FPGA can be developed using the AMD Vivado™ design tool. TEWS offers a well-documented FPGA Board Reference Design. It includes a constraint file with all necessary pin assignments and basic timing constraints. The FPGA Board Reference Design covers the main functionalities of the board.

The TXMC637 is delivered with the FPGA Board Reference Design. The FPGA could be programmed via the on-board Board Configuration Controller (BCC). Programming via JTAG interface using an USB programmer is also possible. In accordance with the PCI specification and the buffering of PCI header data, the contents of the user FPGA can be changed during operation.

Features
  • Standard XMC module
  • User configurable FPGA based on AMD Artix 7™
  • DDR3 SDRAM bank, 256M x 16 bit (512MB)
  • 32 channels 16 bit ADC
    - Offering single-ended and differential mode
    - Programmable input voltage
    - Conversation time: up to 1.1µs
    - Sampling rate up to 1 Msps
  • 8 channels single-ended analog output
    - 16 bit resolution
    - Programmable output voltage: ±10V, ±5.0V or ±2.5V
    - Full scale settling time: typ.1µs
  • 32 digital TTL compatible I/O lines
    - 16 lines optional configurable as differential RS422 interface
  • P14/P16 Rear I/O lines
    - 64 single ended or 32 differential rear I/O lines on a rear XMC 64 pin P14 connector
    - 4 FPGA Multi-Gigabit-Transceiver on a rear XMC P16 connector
Ordering Options
Manuf. Part No    Part Description
TXMC637-10R  Reconfigurable FPGA with 16 x Analog Input 8 x Analog Output and 32 Digital I/O: Artix 7 FPGA (XC7A200T-2FBG676I); 512 Mbytes DDR3; 16 Analog Input; 8 Analog Output; 32 Digital I/O; 64 direct FPGA Back I/O Lines on P14; 4 MGTs on P16

Accessories
Manuf. Part No    Part Description
TA110  VHDCI-100 Cable, 1.2 m
TA201  HD50 / SCSI-2 Terminal Block

Software
TDRV018-SW  Device Driver for Board Family with Reconfigurable FPGA
TDRV018-SW-25   Integrity Software Support
TDRV018-SW-42   VxWorks Software Support (Legacy and VxBus-Enabled Software Support)
TDRV018-SW-65   Windows Software Support
TDRV018-SW-82   Linux Software Support
TDRV018-SW-95   QNX Software Support
Zubehör // Accessories to TOP
TA201

Tews
TA201-10 50-pin Terminal Block 50-pin Terminal Block with 50-pin female SCSI-2 type Connector
The TA201 is used as a standard interface for a switch cabinet to connect a lot of TEWS modules with other system devices. The HD50 Terminal Block is therefore an essential wiring interface for prototyping and in the same way for machine and peripheral equipment ... more
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